The Complementary Metal Oxide Semiconductor (CMOS) technology has been recognized as the leading technology for use in digital electronics in general and for use in many computer products in particular. The miniaturization of CMOS technology according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. Due to the miniaturization of CMOS devices, formation of a contact hole structure with a tight design rule becomes a challenge for manufacturing semiconductor circuits.
FIGS. 1A and 1B are schematic cross sectional drawings showing a prior art method for forming a contact hole structure at an area near to a polycrystalline silicon (“poly”) gate.
Referring to FIG. 1A, a gate 103 and a spacer 105 are formed on a substrate 100. A first dielectric layer 110 is formed over the substrate 100, covering the gate 103 and the spacer 105. An etch stop layer 115 is formed over the first dielectric layer 110. A second dielectric layer 120 is formed over the etch stop layer 115. A patterned mask layer 140 is formed over the second dielectric layer 120, having an opening 130 formed therein.
By using the patterned mask layer 140 as an etch mask, an etch process removes portions of the second dielectric layer 120, the etch stop layer 115 and the first dielectric layer 110 so as to form the contact hole 130a, the second dielectric layer 120a, the etch stop layer 115a and the first dielectric layer 110a shown in FIG. 1B. In the prior art method, the spacer 105 also serves as an etch stop layer by the reason of the tight design rule. Due to the etch process, a portion of the spacer 105 and a portion of source/drain (S/D) salicidation region 150 on the substrate 100 are removed. A recess 130b is formed at the bottom of the contact hole 130a, extending into the S/D salicidation region 150. Due to the lateral width loss d of the spacer 105, the lightly doped drain (LDD) 160a is damaged in the etch process. The source/drain (S/D) region 160b is damaged, too. That is, a substantial amount of material is removed from the LDD region 160a and the S/D region 160b, and the thickness of the regions 160a and 160b is reduced. Without salicidation on the surface of the LDD 160a, the damage at the LDD 160a creates greater leakage currents than that at the S/D salicidation region 150. The leakage currents increase power consumption of the circuits with such a contact structure and cause failure of the circuits.
U.S. Pat. No. 6,489,227 (Hsieh) shows a method for making low-topography buried capacitor by a two stage etching process. The method first deposits oxide layers, and then forms a small pre-contact hole by a dry etch method. A wet etch method forms a large contact hole while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.
U.S. Patent Publication No. 2002/0137355 (GB) relates to a process for forming uniform multiple contact holes. The process features a series of isotropic and anisotropic, dry etch procedures, used to define an initial contact hole opening in the insulator layer, and in the top portion of the conductive region. The isotropic dry etch procedure results in a tapered contact hole profile for top portion of the initial contact hole opening, while subsequent anisotropic dry etch procedures create a straight walled contact hole profile for the bottom portion of the initial contact hole opening. After removal of the contact hole defining, photoresist shape, a wet etch procedure is used to laterally recess the insulator layer exposed in the initial contact hole opening creating the final, uniform contact hole opening.
U.S. Pat. No. 5,216,281 (Butler) is directed to a contact structure incorporating a dopant source. A layer of a transition metal nitride, such as titanium nitride (TiN), is formed over the transistor source, gate electrode, and drain regions. A blanket layer of titanium nitride is formed which covers the top and sides of the dielectric insulated gate electrode, and the bottom and side walls of the openings for the source and drain regions. Where field shield isolation is provided, the nitride layer also covers the top surface of the field shield isolation transistors.
None of these patents address forming a contact hole structure without substantially damaging the substrate.